1. Field of the Invention
The present invention relates to an amplifying type solid-state imaging device and an amplifying type solid-state imaging apparatus including an amplifying type solid-state imaging device. More specifically, the present invention relates to a compact amplifying type solid-state imaging device capable of including an increased number of pixels, and an amplifying type solid-state imaging apparatus utilizing such an amplifying type solid-state imaging device.
2. Description of the Related Art
Currently, the mainstream of the solid-state imaging apparatus is a charge coupled device (hereinafter, referred to as CCD), which is extensively utilized in a variety of fields. In the CCD type imaging apparatus, incident light is photoelectrically converted in a photodiode or a MOS diode. A stored signal charge is transferred to a high sensitive charge release section via a CCD transfer channel, whereby the signal charge is converted into a voltage signal. This results in a high S/N ratio and a large output voltage.
In more recent years, a growing demand exists for a compact imaging apparatus and an increase in the number of pixels. To meet the demand, the size of a pixel must be scaled down. When the size of the pixel is reduced, however, the amount of charge which the CCD can transfer is small resulting in a lowered dynamic range. Furthermore, the increased number of pixels causes a greater power consumption due to the entire device being driven by several phases of clocks as in the case of the CCD.
Recently, to address these problems, an amplifying type solid-state imaging apparatus has been proposed. This apparatus includes a signal charge which is generated in a pixel and is read by a scanning circuit, after the signal charge is amplified in the pixel, without being read in the pixel. In accordance with an amplifying type solid-state imaging apparatus, because the signal charge is amplified, a limitation of the signal charge amount to be read out is eliminated, thus leading to an advantage over the CCD in terms of the dynamic range. Furthermore, it is sufficient to drive only horizontal and vertical line selection switches including signal readout pixels, and a voltage for when the driving is low. Therefore, the power consumption is smaller than that of the CCD.
In general, a transistor is used for amplifying a signal charge in a pixel, and the transistor is classified into an SIT type, a bipolar type and a MOS type.
With respect to the scanning circuit for the signal readout, the MOS type transistor is preferable because the structure of the MOS type transistor is simple and the production thereof is easy. When the MOS type transistor is used for amplifying a signal charge in the pixel, a monolithic apparatus can be produced, thus leading to structural advantages. Furthermore, a single MOS transistor in a pixel is advantageous for increasing the pixel density.
This type of amplifying type solid-state imaging apparatus includes, for example, a TGMIS (Twin Gate MOS Image Sensor) type. One example thereof was previously proposed by the-Applicant in Japanese Patent Application No. 6-148330 (corresponding to the copending U.S. application Ser. No. 08/382,257). FIGS. 15A and 15B show the prior art pixel structure thereof, namely, the structure of the amplifying type solid-state imaging device.
As shown in prior art FIG. 15B, a first gate electrode 2 and a second gate electrode 3 are formed on a p-type semiconductor substrate 1 via an insulating film. N-type well layers 4 are suitably spaced in a horizontal direction on surface portions of the semiconductor substrate 1 and below the first gate electrode 2. N.sup.+ diffused layers are suitably spaced on surface portions of the well layers 4. One of the pairs of the n.sup.+ diffused layers constitutes a source 5 of a MOS type transistor using the first gate electrode 2 as the gate thereof, and the other n.sup.+ diffused layer constitutes a drain 6.
In the amplifying type solid-state imaging device having such a structure, incident light h.upsilon. which has penetrated the first gate electrode 2 generates electron-hole pairs by photoelectric conversion, such that electrons drift to the drain 6. On the other hand, the holes are confined in a potential barrier formed in an intermediate region of the well layer 4 and a potential barrier below the second gate electrode 3, and stored at the semiconductor/insulating film interface of the well layer 4 so as to become signal chargers.
The amount by which the potential of the well layer 4 is varied depends on the stored signal charge amount, which is read out as an amplified electric potential variation in the source 5, and used as an output signal.
The release of the signal charge is readily achieved by lowering the potential barrier below the second gate electrode 3 so that the signal charge drifts to the semiconductor substrate 1 along the path shown by the arrow in FIG. 15B. More specifically, the holes stored as the signal charges flow from the surface region of the well layer 4 to the semiconductor substrate 1, and thus the signal charges are reset. In the present specification, the release of the once stored signal charges is referred to as `a reset operation`.
Next, the operations during signal charge storage, signal readout and release of the signal charges will be described in details with reference to FIGS. 16A, 16B and 16C. Herein, the right side of each of FIGS. 16A, 16B and 16C shows a depth direction potential distribution below the first gate electrode 2, and the left side of each of FIGS. 16A, 16B and 16C shows a depth direction potential distribution below the second gate electrode 3.
First, the operation during the signal charge storage will be described with reference to FIG. 16A.
A low voltage VGA(L) is applied to the first gate electrode 2, and a medium voltage VGB(M) is applied to the second gate electrode 3. Thus, a potential barrier .DELTA..phi.B of a predetermined value or more when against holes, is formed below the second gate electrode 3. The potential barrier prevents the holes from flowing from the semiconductor substrate 1 to the surface of the well layer 4. The value of the potential barrier .DELTA..phi.B is about .about.0.5 V (i.e., a value lower than and close to 0.5 V) in the case where the semiconductor substrate 1 is silicon. The description below will be limited to the case where the substrate is silicon.
The holes generated by photoelectric conversion are stored on the surface of the well layer 4 as signal charges, and the potential distribution on the surface of the well layer 4 is raised from state (1) to state (2). During the period when a difference .DELTA..phi.AB between the surface potential of the well layer 4 and the surface potential below the second gate electrode 3 is large (ie., .DELTA..phi.AB&gt;0.5 V), the signal charges stay on the surface. However, when the signal charges continue to be stored, the potential distribution is further raised and reaches the storage limitation state as shown in state (3). In this storage limitation state, .DELTA..phi.AB is smaller than .about.0.5 V, so that the stored holes jump the potential barrier below the second gate electrode 3 and flow to the semiconductor substrate 1. Thus, excess charge can overflow, thereby making it possible to prevent blooming . Herein, the potential depth of the n-type well layer in the state (2) is designated as .DELTA..phi.A(Sto).
Next, the operation during signal readout will be described with reference to FIG. 16B.
A high voltage VGA(H) is applied to the first gate electrode 2. Thus, a potential distribution below the first gate electrode 2 is further raised. When there is no signal charge, the potential distribution is in the state (4). When signals are being stored, the potential distribution is in the state (5), The potential depth of the n-type well layer in the state (4) is designated as .DELTA..phi.A(Det). Herein, the value of VGA(H) is selected so as to satisfy an inequality .DELTA..phi.A(Det)&gt;.DELTA..phi.A(Sto).
On the other hand, a high voltage VGB(H) is applied to the second gate electrode 3. Thus, a potential barrier higher than the surface potential of the well layer 4 during the signal storage by .DELTA..phi.AB (&gt;0.5 V) (in the state (5)) is formed below the second gate electrode 3. The high potential barrier prevents the signal storage charges from flowing from the surface of the well layer 4 to the semiconductor substrate 1.
When the value of VGA(H) is set so as to satisfy the requirement of .DELTA..phi.A(Det)&gt;.DELTA..phi.A(Sto), the signal readout of a selected pixel is only performed for the following reason. Even if a source terminal VS (as shown in FIG. 15A) is connected to a plurality of common pixels, a VGA(H) is applied to a specific gate and VGA(L) is applied to other gates, and the inequality of .DELTA..phi.A(Det)&gt;.DELTA..phi.A(Sto) is satisfied, the source electric potential to be detected is defined by the value of the source terminal corresponding to the VGA(H) gate.
Next, the operation during reset will be described with reference to FIG. 16C.
A high voltage such as VGA(H) in the signal readout, is applied to the first gate electrode 2, and a medium voltage, such as VGB(M) in signal storage, is applied to the second gate electrode 3. At this point, the potential below the second gate electrode 3 is a value (-.DELTA..phi.AB) sufficiently lower than the surface potential of the well layer 4 when there is no signal charge (i.e, in the state (4)'). For this reason, all signal charges, i.e., holes on the surface of the well layer 4, pass below the second gate electrode 3 and are released to the semiconductor substrate 1. In other words, a reset operation is performed. Thus, once image information is cleared, an operation of storing subsequent image information can be performed. Furthermore, when the reset operation is performed in the middle of the period during optical integration, the image information prior thereto is cleared, and the information after that point is stored, Thus, a so-called `shuttering operation` can be performed.
However, in the TGMIS amplifying type solid-state imaging apparatus having the structure shown in FIGS. 15A and 15B, when a pixel area is reduced for the purpose of increasing pixel density, the following problems arise. The problems will be described with reference to FIGS. 17A and 17B. FIG. 17A is a cross sectional view similar to FIG. 15B. FIG. 17B shows a depth direction potential distribution below the first gate electrode 2 and a depth direction potential distribution below the second gate electrode 3 during the reset operation.
To increase the pixel density and reduce the pixel area, and to realize a further increase in the number of pixels and further compactness in the amplifying type solid-state imaging device used in the above-mentioned TGMIS amplifying type solid-state imaging apparatus, it is necessary to further reduce the width of the second gate electrode 3 and a space between a source 5 where an output signal is detected and a drain 6.
However, when the sizes thereof are reduced to some extent, a three-dimensional potential ridge 7 is formed in the path through which the stored charges are released by an electric field which is generated by an electric potential applied to the source 5 and the drain 6. For this reason, even if the surface potential barrier below the second gate electrode 3 is lower than the surface potential below the first gate electrode 2, as shown on the left side of the FIG. 17B, the potential ridge 7 is formed in the intermediate portion between the surface of the bulk of the potential distribution below the second gate electrode 3 and the semiconductor substrate 1. Therefore, the holes which are stored as signal charges cannot flow anywhere. As a result, the stored signal charges cannot be completely released to the semiconductor substrate 1.
In order to prevent the potential ridge 7 from being formed, when the electric potential of the source 5 and the drain 6 is set at 5 V, the width of the second gate electrode 3 can be set at, for example, 3.5 .mu.m or more. However, when the width of the second gate electrode 3 is set at this, it is difficult to realize high pixel density and miniaturization of the apparatus. For this reason, according to the amplifying type solid-state imaging device having the structure shown in FIGS. 15A and 15B, the attempt for the high pixel density and miniaturization of the solid-state apparatus was subjected to some constraints.